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Home IC Layout Training IC Layout Training Courses. This course focuses on the layout of devices used in ESD protection schemes for ICs. Content includes device compositions, parasitic effects of ESD structures, isolation schemes, and whole chip ESD protection methodologies. Coursera and Udemy come to mind. The first answer to this question has a linke for coursera, so here is one for Udemy: Master VHDL Design for use in FPGA and VLSI Digital Systems Googled it and found also something on iTunes: Digital Electronics &.
In this book Chip Design we tell how to build an integrated circuit ('chip') by integrating billions of transistors to achieve an application. An application could be suiting a particular requirement like microprocessor, router, cell phone,etc. Contents.Before Designing a Chip?
Need to Brain Storm. What market is the Chip targeted for?. What are the Protocols involved in the Chip?. What is going to be our Processor/Bus Architectures?.
What is the power/IR-drop/timing/area/yield targets and how to budget it in the Chip?. What is the process in which the Chip is going to be manufactured?. What are the various third party IP's/Memory requirements?. What is our design flow, EDA tools and methodology involved?.
What is the estimated Chip cost?. Above all, the bottom line of any business model is money. What is our Profit model? What is our estimated ROI (Return of investment)?Analogy of Chip Design Architecture Vs Building Architecture. Why an Analogy with Building Architecture? To understand the concepts of Chip designing in a better way, as we are very familiar with Building Architecture, then it will be easy for us to map Chip Design architecture.VLSI (Very large scale Integration) flow was evolved similar to the flow involved in Building Construction.
Now let us delve in to the construction flow to better understand the VLSI Chip design flow development.Whenever we start to construct a building, we will have an architecture, how the building should look like, the exterior looks, etc. Similar to that we will be designing an architecture in the chip-design, based on the requirement of the product, what the product is addressed for and whom to serve what needs -the so called specification- of the different modules.Now lets go in to the implementation part of both the Building & Chip.We at first come with the floorplan of the building, similarly we come with the floorplan of the Chip. Based on the connectivity/accessibility/vaasthu we place our rooms, similarly we have the constraints to place the blocks.
Like we build the building with bricks, windows and other modules, for Chip Design we have component libraries, which are like pre-designed bricks, for a specific functionality.Now let us try to understand the power-structure or electrical connectivity in our building. Initially we have an electrical plan for our building, where we have a requirement that all our electrical gadgets needs to get power. Similar to that we have a Chip power requirement. The required power is supplied through the power-pads, over a ring-like topology to have a uniform distribution across all corners of the chip, and the supply has to reach all the standard-cells (bricks for Chip-Designing), this is called as power-grid topology in the Chip-Design. Now the requirement is how well we design our Power-grid to reduce the IR-drop, so that our standard-cells get proper power requirement.I would not make justice if I don't discuss about clock and clock-tree in the Chip-Design flow. We have synchronous and asynchronous (more difficult to test and verify) ways of designing. The majority of chips follow a synchronous design, for which Static Timing Analysis is possible.
For the relevancy of the flops, the clock signal from the crystal should reach at the same time -or within some skew targets- to different components within the chip. In order to make this happen, a step called clock-tree is performed after power-grid is created.Let us try now to visualize the concept behind Place & Route in Chip Design, where the different components of the chip are physivally placed and their pins properly inter-connected. To have a better understanding of this concept, let us assume a society where people speaking different languages are living together, and let us visualize how people talking the same language will tend to end up living in the same neighborhood, forming separated communities and making the communication between people much easier. In a similar way, in chip-designing, standard-cells having strong relationships are placed closer in the placement flow, forming separated areas. This process is called as regioning. Now, within the regions, the standard-cells which are really sharing data have to be placed close-by so that their timings match and are optimized. This step is called placement, while defining the connectivity across the standard-cells is called as routing, and the challenge is having optimized or reduced wire-lengths.Now let us try to understand the concept behind Signal Integrity (SI) in the Chip-Design, often called as SI Effect.
As our processes are shrinking day by day, and our silicon-realestate is costly, we try to accommodate more and more standard-cells in a limited area, so the cells are placed in very close proximity, and the switching of one cell can have an impact over the others' behaviour, which can make the path to be faster or slower. This issue is called as signal-integrity. So similar way in our construction in order to maintain the integrity with in the house (neighbour free-zone), within the limited zone of modurality, we try to create fences across buildings, similarly we can think of a concept called as Shielding, the high frequency signal net with the power-nets running across.
We perform spacing across the buildings, similar way we can perform spacing across the nets, which are in close proximities.In order to validate the silicon from the manufacturability issues, the concept in the Chip Designing is Design for Test(DFT). One of the DFT techniques is scan-chain.